As shown in FIG. 1, a prior art synchronous memory device 40, such as a synchronous static random access memory (SSRAM), includes as its central memory element a memory array 42 that contains memory cells arranged in rows and columns. The array 42 is divided into four quadrants 43.sub.1 -43.sub.4, each of which is divided in turn into eight segments 45. Each segment 45 includes 16 pairs of column lines intersected by several row lines, and the memory cells are coupled at intersections of the row and column lines.
A controller 44 controls reading from and writing to the array 42 in response to a clock signal CLK and commands READ, WRITE, as shown in the first and second diagrams of FIG. 2. The clock signal CLK and commands READ, WRITE are supplied at input terminals 47 from a source external to the memory device 40 such as a memory controller (not shown in FIG. 1). One skilled in the art will recognize that the commands READ, WRITE are actually a composite of signals, such as a row address strobe RAS*, a column address strobe CAS*, and a write enable signal WE*.
Within the memory device 40, the controller 44 controls reading and writing by producing internal control signals such as a write recovery signal WR* and a write data signal WD*, in response to the commands READ, WRITE. As will be explained below, the write data signal WD* enables writing to the array, and the write recovery signal WR* initiates precharging and equilibration to prepare the array for subsequent reads or writes. One skilled in the art will recognize that the asterisks following the signals WR*, WD* indicate that the signals are low-true signals. That is, the signals WR*, WD* are low voltages when true.
In addition to the externally supplied command signals READ, WRITE and clock signal CLK, the memory device 40 also receives addresses AN from an address bus 46 at an address buffer 48 and receives and outputs data from a data bus 49 with input and output data latches 64, 66. The addresses AN received at the address buffer 48 may be row or column addresses. If an address is a row address, the address is stored in a row latch 52. The row latch 52, under control of the controller 44, then transmits the row address to a row decoder 62. The row decoder 62 decodes the row address and activates a corresponding row of the memory array 42 in response to the internal control signals from the controller 44 and the clock signal CLK, as will be discussed in greater detail below.
If the address A.sub.N is a column address, the address A.sub.N is stored in a column latch 50. The column latch 50 forwards the address A.sub.N to a column decoder 54. The column decoder 54 decodes the address A.sub.N and provides the decoded address to a column selector 60 in an I/O interface 56. In addition to the column selectors 60, the I/O interface also includes I/O elements such as sense amplifiers and precharge circuitry in a bank of driving circuits 58, where each driving circuit 58 corresponds to one segment 45 of the array 42. Each driving circuit 58 outputs signals to or receives signals from the respective column selector 60 on a respective pair of complementary data lines 76. In response to the decoded address A.sub.N from the column decoder 54, the column selector 60 couples the pair of data lines 76 to one of the 16 pairs of complementary digit lines in the corresponding segment 45.
In a read operation, a read command READ and an address A.sub.1 specifying the location of data to be read are received at time t.sub.1, as shown in FIG. 2. The logic controller 44 then determines that an operation is a read operation and outputs a word line signal WL to activate the addressed row line at time t.sub.2, as shown in the fourth diagram of FIG. 2. Shortly thereafter, at time t.sub.3, the column decoder 54 provides the decoded column address A.sub.1 to the column selector 60, as shown in the fifth graph of FIG. 2. In response, the column selector 60 couples the corresponding pair of data lines 76 to one pair of digit lines. One skilled in the art will recognize that the row line and column line activated at times t.sub.2, t.sub.3, respectively, may correspond to an address and command received at a clock pulse preceding time t.sub.1, depending upon the latency of the device 40. It is assumed for simplicity herein that the device is a two-latency device, so that the row and column signals WL, COL at times t.sub.2, t.sub.3 correspond to the row address, column address and write command present at time t.sub.1.
At time t.sub.4, the controller 44 activates the I/O interface 56 to cause the sense amplifiers to read the data on the selected digit line and provide the data to the output data buffer 66. At time t.sub.5, the output data buffer 66 makes the output data available at the data bus 48.
In a write operation, a write command WRITE and an address A.sub.2 specifying the location where data is to be stored are received at time t.sub.6, as shown in FIG. 2. The controller 44 enables writing at time t.sub.7 by providing a low write data signal WD* on a write data line 70. Then, at times t.sub.8, t.sub.9, respectively, the controller 44 activates the row decoder 62 to activate the corresponding row of the array 42 and activates the column decoder 54 to provide the column address to the column selector 60.
In response to the write data signal WD* and data from the input data buffer 64, one of the driver circuits 58 outputs data on its pair of data lines 76. The column selector 60 transfers the data from the pair of data lines 76 to one of the 16 pairs of digit lines in the corresponding segment 45. Because the corresponding row line is active, the data are written to the location in the memory array 42 corresponding to the address A.sub.2.
After a sufficient time has elapsed for writing data, the column signal and row signal WL returns low at times t.sub.10, t.sub.11 to deactivate the column and row. Then, at time t.sub.12 the write data signal WD* returns high (not true) to terminate writing by the local driver circuit 58. Shortly thereafter at time t.sub.13, the controller 44 provides a low-going pulse of the write recovery signal WR* on a write recovery line 72. The pulse of the write recovery signal WR* activates precharge circuitry in the local driver circuit 58 to precharge the column lines. In response, the driver circuit 58 sets the data lines 76 high The high data lines 76 raise both digit lines in the pair to a high voltage, because the column selector 60 is still active. After the driver circuit 74 charges the data lines 76, the column selector 60 decouples the data lines 76 from the selected digit lines. The pair of digit lines are thus raised to high voltages to prepare for subsequent reading.
One problem with the above-described approach is that the write recovery signal WR* does not begin until the write data signal WD* ends. The controller 44 must therefore allow time between the end of the write data signal WD* and the arrival of the next clock pulse for the write recovery signal WR* to initiate recovery of the digit line voltages. If the controller 44 does not allow sufficient time for the write recovery signal WR*, the write recovery signal WR* may still be low after the end of the writing period (i.e., after the next leading edge of the clock CLK). Consequently, the driving circuit 58 may still be precharging the lines at the same time that the device is attempting to read data from the array 42. The precharging circuitry will thus write a cell to a high voltage, regardless of its original data.
Another problem with the prior art circuit shown in FIG. 1 arises from the distance traveled by the pulse of the write recovery signal WR* along the write recovery line 72 to the most distant driver circuit 58. As the pulse propagates, capacitive and resistive effects may limit the speed at which the pulse can raise the voltage of the driver circuits 58. The controller 44 must therefore provide the write recovery signal WR* for a sufficiently long period to raise the voltage at the most distant driver circuit 58 above a minimum value (typically a threshold voltage of a precharge or equilibration transistor). The overall clock period must be long enough to accommodate the write recovery signal WR* after the write data signal WD* goes high, thereby lowering the overall clock frequency.